- Industry Standard Architecture, ISA may also refer to Instruction Set Architecture.
The Industry Standard Architecture (ISA) bus was created for the original IBM PC back in 1981. At that stage, it was an 8-bit, 5MHz bus (2.39MB/s), but was later upgraded to 16-bits at 8MHz (8.33MB/s). Today, the ISA bus is archaic and incredibly slow, but it is still commonly found in older machines, and many of the most common, basic devices are connected to it. For this reason, it is still supported by many operating systems. It is slowly being replaced by the Super I/O chip that is common amongst modern machines. For more information on the history and implementation details of the bus, visit the Wikipedia page on the subject.
There are broadly four types of resources that cause device conflicts (listed in the order problems are generally experienced):
Managing these resources becomes the responsibility of the operating system. Fortunately, Microsoft has created a standard called Plug-and-Play (PnP) that helps with this. Not all ISA cards support it, however, so some luck is required in that the person building the system has set the correct jumpers.
The ISA bus can support x86 16-bit port addresses, but many older ISA cards only support 10-bit address decode. This presents a major problem that can lead to conflict. When the processor tries to access a certain resource on the ISA bus, it will signal all ISA devices in the hopes that only one responds. If a card can only handle ten of the address bits, it can respond to IOR and IOW signals when it should not be, because it does not see the upper bits.
So if a device is located at port 100H, that 10-bit address with every possible combination for the upper 6 bits will map to the same device (e.g port 0xFF00). To make this totally impossible, one can simply restrict PnP port addresses to be within the 1024-byte range to make such conflicts impossible, though this would be a limitation.
The decode of legacy devices like the LPT, COM, etc. that are typically embedded in the mainboard are probably 16-bit on PnP boards, but checking with the BIOS is the only way to be sure.
ISA Plug-and-Play Overview
The original ISA bus, or more specifically, the 16-bit PC/AT bus used static non-sharable resource assignments and had no isolation between cards. There was no way to program it from software. A number of buses appeared on the PC market such as VLB, PCI, and EISA. These architectures were incompatible with the original design. Plug-and-play ISA was introduced to get around the original limitations while maintaining compatibility and improving user friendliness. The following is a general overview of the ISA Plug-and-play specification. The goal of this section is to clarify the documentation as there are many forward references to the appendices. See the original document (ISA PnP 1.0A) for more authoritative information (including timeouts).
Developers looking for robust support for the 1990's generation of hardware may want to add plug-and-play ISA support.
I/O Ports and Initiation
There are three 8-bit ports specified by the ISA PnP standard that are used for accessing configuration spaces.
|0x279 (Same is LPT status, but W)||ADDRESS||W|
Note: Each of these ports use 12-bit decode
The ADDRESS port is an 8-bit port that takes two bytes. The first byte send is the CSN, or card select number. The second is the offset in the configuration space. The address is the same as the printer status, but ports are bidirectional on PCs.
Cards in PnP mode are disabled on startup and are in a "Wait for Key" state. Once configured, they should be returned to this state. The Initiation Key is a 32-byte sequence sent to the ADDRESS port that will put the cards in configuration mode. Send zero twice to clear any previous address before sending this key.
; Warning: not tested SendKey: pushfd ; Save IF cli cld mov dx,ADDRESS mov esi,Key mov ecx,32+2 rep outsb popfd ; Restore IF, nothing else changed ret
The key is defined as:
Key: ; Zero bytes to clear ADDRESS DW 0 ; The actual key DB 0x6A,0xB5,0xDA,0xED,0xF6,0xFB,0x7D,0xBE DB 0xDF,0x6F,0x37,0x1B,0x0D,0x86,0xC3,0x61 DB 0xB0,0x58,0x2C,0x16,0x8B,0x45,0xA2,0xD1 DB 0xE8,0x74,0x3A,0x9D,0xCE,0xE7,0x73,0x39
AMD recommends (PCnet-ISA II 3) disabling interrupts while performing the IO operation to prevent anything else from interfering (as shown above). No other ports should be accessed. Although not mentioned in the original specification, it is also recommended by AMD to send it twice in case the key is not received the first time.
Isolation and CSNs
The specification details isolation of cards. BIOS is supposed to perform this procedure. The term "plug-and-play software" in the specification may refer to the OS and firmware. On startup, the BIOS will send the initiation key, perform the serial isolation procedure, and take the cards out of isolation or configuration mode and have them wait for key. Each card is assigned a sequential handle starting from 1 called a CSN. The number of CSNs that the BIOS assigned, as well as the READ_DATA port that the BIOS decided can be found with PnP function 40h.
Despite the BIOS performing isolation itself, the PnP BIOS specification says that the OS should not rely on the BIOS at all and do it again.
Card Control Space
Appendix A specifies the card-global configuration space. Here is an overview of what the card control section looks like:
|Offset||Name||What it does|
|0x00||Set READ_DATA||Set the READ_DATA address|
|0x01||Serial Isolation||(TODO: Add this)|
|0x02||Config Control||See below for spec|
|0x03||Wake[CSN]||Writing here wakes that CSN|
|0x04||Resource Data||Reading fetches the next byte|
|0x05||Status||If bit 0 is set, it is safe to read data|
|0x06||Card Select Number||The CSN, can be changed|
|0x07||Logical Device||Selects a logical device, read-only zero if none|
Note: Some operations appear to be global in scope
Waking Up Cards
If it is not clear, writing to the Wake[CSN] port sets the actual CSN to perform the wake operation. This is required in the isolation procedure.
The Set READ_DATA register (also referred to as RD_DATA) is an 8-bit value that relocates the READ_DATA port to the range specified above. This value is practically shifted left by three and or'ed with "11" in binary (Page 15) to create a 10-bit address slanted by 3. The value written to this register would be:
Set_READ_DATA = (PhysicalPort & 0x3F8) >> 3 /* Make sure first bits are 11 */
E.g. writing 0x40 to this port will place the READ_DATA port at 0x203
Reading this register does nothing, the programmer must assign this port and check for conflicts. There is only one for all cards.
Resource data is read from the dedicated register for the logical device selected. Bit zero of the status register must be polled until it is one before reading the resource data. The resource data register is READ ONLY. This resource data is not to be confused with the resource configuration registers in the card control space. It defines what resources the card is able to use. If a fully PnP card uses any memory address range, the static resource entry will be 0x00000000-0xFFFFFFFF (AFAIK), and the same applies to ports, DMA, and IRQs. If only one DMA or IRQ is implemented, that device must use it. For IO ports, the tag can be a fixed descriptor or regular one. If the tag is a fixed descriptor, the old 10-bit ISA decode is used for that range.
The PnP ISA specification allows for 32-bit data and addresses. This is definitely not used by any ISA cards because the ISA bus is 16-bit and only supports 24-bit addresses. Despite this, the OS should support this by indirection for consistency.
The PnP BIOS uses the same format for reporting devices connected to the mainboard.
Logical Device Local Control
The logical card control registers are found at 0x30-0x3F. This space is present on all cards, even if they do not have any logical devices. Selecting the logical device swaps out this space. To check if the card is multi-function, write a value other than zero to the logical device register and try to write it back. If a read of LDS still generates a zero, the device has no functions. Otherwise, write back the original value (zero i.g.).
The activate register turns on the card or the logical device belonging to that card when the first bit is on. If there are no resources for a card, the OS will have to disable the card by setting the register to zero (the user should be notified). IO range check should be disabled while activating.
The resource data is stored in the logical card space. The memory information starts at 0x40 or 0x76 and is seen at Table A-3. Memory descriptors are four bytes for 24-bit addressing and nine for 32-bit. The specifics are detailed in A.3.1.
Supporting ISA PnP
PnP ISA devices can suport varrying levels of configurability. For example, a card that implements a parallel port may only be configurable to three standard addresses for PC compatibility. The static resource data mentioned previously reports what data a device supports, but not necessarily what it will use.
The plug-and-play management code of the OS must be able to handle every possible bus, and combinations of buses, as some computers have PCI and ISA. Reserving resources should be supported so that less-so or non-configurable devices can work.
The following specifics of ISA PnP must be implemented in the operating system:
- Memory address ranges supported
- IO port ranges
- Address and port decode
- Data width (8/16/32-bit)