PCI Local Bus Commands

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This page seeks to describe the PCI local bus commands -- these commands are sent over the C/BE signal pins from a master to a target.

This page is not meant to be an exhaustive description but rather a quick refresher for the use of someone who has already read the PCI Local Bus specification. This page references signals documented in this article here and recommends it as prior reading.

PCI C/BE commands

All commands except for the Configuration commands are optional. All devices other than host bridges are _required_ to respond to configuration commands.

C/BE Value Name Short Description
0b0000 Interrupt Acknowledge
0b0001 Special Cycle
0b0010 I/O Read
0b0011 I/O Write
0b0100 Reserved
0b0101 Reserved
0b0110 Memory Read
0b0111 Memory Write
0b1000 Reserved
0b1001 Reserved
0b1010 Configuration Read
0b1011 Configuration Write
0b1100 Memory Read Multiple
0b1101 Dual Address Cycle
0b1110 Memory Read Line
0b1111 Memory Write and Invalidate

General requirements

Memory commands

  • IF a target implements the memory read/write commands, then it must support all of them, whether explicitly or by emulating the more complex ones internally by mapping them behind the scenes to repetitions of the basic ones.
  • Devices between the master and the target (including the master and target) which prefetch data into a buffer or otherwise cache data to present burst behaviour must conform to the PCI specification's constraints on "prefetchable vs non-prefetchable memory". Prefetchable memory is defined as follows:
    • When read, it has no side effects (such as advancing a hardware cursor in a device register, or acknowledging an interrupt).
    • Bridge devices between the master and target may merge reads together harmlessly.
    • When being read, the target may safely return all bytes in a DWORD irrespective of the Byte Enables.
  • For the cache-line read/write commands, the target must read/write to the end of the containing cache line and not beyond, irrespective of whether or not the offset of the read/write was aligned to the beginning of said cache-line.
  • If a master is reading/writing from/to a target which does not implement the Cacheline-Size register, the master should assume a cache line size of 16 or 32 bytes and proceed accordingly.


  • A bridge between a master and target which prefetches is responsible for discarding/invalidating prefetched data which ends up not being consumed by the master. The second "Implementation Note" in section 3.1.2 strongly implies that a PCI master should be able to poll a memory address and not worry about receiving stale data from the bridges between itself and the target.

Caveats for each command, if they exist

Memory Read Line and Memory Read Multiple

  • The master assumes the burden of knowing whether or not the desired address range is prefetchable, which allows any bridge between the master and target to prefetch. Burst read/write commands should not be issued to a non-prefetchable range.
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