Talk:8259 PIC

Discussion Topics:

Masking

Shouldn't the masking function be in one function? Also, shouldn't we have a topic about all the registers of the PIC? Primis 19:53, 27 February 2011 (UTC)

No, having the masking done in two functions shows clearly what needs to be done. Also, Primis, please make sure any edits you make are actually correct. I have reverted your "fix" to the IRQ number checks. Thepowersgang 23:49, 27 February 2011 (UTC)

Well there are 8 IRC lines per PIC, but they start at zero, so the first PIC is 0 ... 7 and the second is 8 ... 15. However the function is not Greater than or Equal to (>=) but is just greater than (>) so the function is gonna be out of sync no? Primis 01:55, 1 March 2011 (UTC)

The operation is < in this case, 0 - 7 are less than 8, so they should they use the first controller. The current code is correct. Thepowersgang 04:16, 1 March 2011 (UTC)

History

I'm not sure, but, I remember that Norton says about 16 hardware irq's in PC. 418imateapot

{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15} is a set of 16 numbers; yes. There are 16 hardware IRQs.

io_wait

The PIC_remap function makes use of an io_wait function -- any suggestions as to how to implement this function? read a port?Clearer 10:18, 16 December 2011 (UTC) Nevermind: http://wiki.osdev.org/Inline_Assembly/Examples

Don't - the IO delays are unnecessary in general (on 80486 and later) and especially unnecessary in that example code (as you're interleaving IO port accesses to different chips) --Brendan 21:16, 16 December 2011 (UTC)

Suggestion

Shouldn't the abstract theory surrounding a "Programmable IRQ/Interrupt Controller" and then the concrete example of the i8259 chips be separated? Would like to suggest not redirecting "Programmmable Interrupt Controller" to this page, and creating a separate article for it. Gravaera 07:50, 13 June 2012 (CDT)

Does any other hardware have a PIC that's generally called just PIC?

general usage of IRQ numbers

I'm missing a table of what the general usage for each interrupt number is. E.g. 12 is PS2 Mouse. This could link to http://wiki.osdev.org/index.php?title=Interrupts#Standard_ISA_IRQs

Disabling

Is there a reason this is written in assembly and hard coded, rather than using the functions consistent with the rest of the article?

mov al, 0xff
out 0xa1, al  // outb(PIC1_DATA, 0xFF);
out 0x21, al  // outb(PIC2_DATA, 0xFF);

ICW4 and other macros

The article says in the #define comment for ICW1_ICW4 that ICW4 is not needed, but this macro is used when sending ICW1. Tree5678 03:05, 3 July 2022 (CDT)

I think it actually is needed and the comment is misleading. If I understand it correctly, X86 CPUs need the PIC to be in 8086 mode (the PIC seems to assume by default that it's connected to an 8080 CPU which needs some slightly different signals, so the mode needs to be changed in ICW4). So here's how I understand the code

• Send an ICW1, which tells the PIC that we want to initialize it and that the initialization will include a fourth control word (ICW4). And send it to both PICs.
• Send an ICW2, setting the offset of the interrupts. So line n triggers interrupt n + offset_x, where we want each PIC to have a different offset so that we can tell which PIC an interrupt is coming from.
• Send an ICW3 to each PIC, telling each one that the other one exists.
• Send an ICW4 to both PICs telling them to use the 8086 mode.

I suppose I could at least change the comment to mention that ICW4 is needed, and add a comment where the ICW4 gets sent to the master PIC (since we're sending the same to both PICs, I suppose that repeating the comment would be redundant).

I hope this makes sense. I think I understand what those control words are doing, but I'm not sure how readable my explanation of it is. - SeaLiteral (talk) 12:54, 30 March 2023 (CDT)