User:Gravaera/PCI Local Bus Device Adress Spaces

Prologue

This page seeks to provide a quick reference for a person who has already read the PCI Local Bus Specification and is not meant to serve as an exhaustive description of the PCI Local Bus.

Address Configuration for device address space blocks

PCI devices may export one or more address space blocks or regions. The device must specify for each block, the size of the block and which address space it must be allocated into by the host OS software. The device does not determine where within the requested address space it will end up being allocated to. The address allocated by the host OS is written into the device's BARs (Base address registers).

PCI SIG cautions creators of new devices to prefer to request blocks in the Memory Address space and not the I/O address space since this will increase their portability.