User:Gravaera/Xilinx Ultrascale+ MPSoC
The SoC has a CSU (Configuration and Security Unit) ROM. This ROM is executed first followed by a PMU Pre-boot ROM (See Ch 37 "Basic Clock Generators"), and then the CSU Boot ROM samples the "mode pins" (asserted by the chipset) which tell it which internal storage device should be used as the boot device for the FSBL (First Stage Boot Loader). The FSBL is packaged with some headers which tell the CSU ROM software about how to load it.
After FSBL begins executing the CSU ROM software goes resident and monitors the running system for "tamper signals" from "various sources [sic] in the system".
Power management for the SoC is done through the PMU (Power Management Unit) which takes requests to power up and down peripherals and also is used to enable and disable clocks and resets.
The Processing System (The traditional general purpose computing platform) and the Programmable Logic (The FPGA embedded into the SoC) go by those names. The PS and PL are connected by means of an AXI Cache-coherent Interconnect which is called the "AMBA Interconnect".
There are 5 top level clock sources in the clock tree; these are called the PLL source clocks because they pipe into the 5 top level PLLs. They are:
- PS_REF_CLK (Device pin, normal source)
- ALT_REF_CLK (Its source is chosen from one of two MIO pins)
- VIDEO_REF_CLK (Its source is chosen from one of two MIO pins)
- AUX_REF_CLK (Its source is within the PL Fabric)
- GTR_REF_CLK. Its source is an multiplexer output from one of the four GTR inputs to the SIOU -- these four are:
- 0: PCIe/USB.
The PS subsystem has two power domains: the LPD (Low Power Domain) and the FPD (Full Power Domain). There are two top-level PLLs within the LPD and three top level PLLs within the FPD, for a total of 5 top-level PLLs within the PS subsystem. These 5 PLLs are called:
- RPLL_CLK: RPU (Realtime Processing Unit -- Cortex R .Little cluster of the Big.little arrangement) PLL.
- IOPLL_CLK: IO Peripheral PLL.
- APLL_CLK: APU (Application Processing Unit -- Cortex A Big cluster) PLL.
- VPLL_CLK: Video PLL (GPU and video codec unit).
- DPLL_CLK: DDR PLL.
There are however, 5 divisors within each of the power domains for a total of 10 divisors. The outputs from all 5 top-level PLL are split up and piped into the 5 divisors in both power domains such that both power domains have access to the outputs from all 5 PLLs, supplied to them as inputs to their 5 respective divisors. The divisors which reside in power domains that are different from the power domain that their PLL source resides in are called "power domain crossed clocks".
The 5 divisors then pipe into various "clock generators" which are piped into various peripherals and IPs.